# Set Library
set target_library "/projects/pdk/umc28/stdcell/DesignWare_logic_libs/umc28nlph/35hd/hdl/lvt/3.00a/liberty/logic_synth/um28nphllogl35hdl140f_ssgwc0p81v0c.db"
set tjroc_home "/projects/lhy/tjroc"
set search_path "$search_path /projects/lhy/tjroc/src"
set link_library "* $target_library"
set synthetic_library "dw_foundation.sldb"

# Read Verilog
analyze -format verilog {SmartRouter.v BypassMux.v Allocator.v Arbitor.v BufferWrArb.v NxtRtrComp.v SwAlloc.v SwTrav.v LkAheadGen.v LkAheadRtrComp.v LkAheadConflict.v VcAllocNby.v VcMux.v SyncFifo.v}
elaborate SmartRouter

# Constraints
create_clock -name clk -period 10 [get_ports clk]
set_input_delay -clock clk 2 [all_inputs]
set_output_delay -clock clk 2 [all_outputs]

# Compile
compile

# Area
report_area

# Save results
write -format verilog -hierarchy -output CurryALU_syn.v
write_sdc CurryALU_syn.sdc
exit